An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAs

We discuss an estimation and simulation framework for energy efficient application design using platform FPGAs. This framework integrates various widely used simulators available for platform FPGAs, allows specification of kernel designs as a set of libraries, and enables efficient application design through the integration of high-level performance estimators and design space exploration tools. This framework is based on the concept of Model Integrated Computing and provides a flexible, extensible, and plug-nplay environment for application design. 1. Background and Motivation Platform FPGAs integrate (within the FPGA fabric) processors for system control and DSP cores for customized data filtering and parallel processing [8]. These devices offer several design choices such as operating frequency, precision, amount of memory, degree of parallelism, clock gating, implementation alternatives, etc. These choices define a large design space that must be efficiently explored to find suitable solutions. Adaptive beam forming,multi-rate filters and wavelets, software defined radio, etc. are some of the target applications for platform FPGAs. These applications are compute intensive and multi-functional, are expected to satisfy hard latency constraints, and many of them are candidates for deployment in power constrained environments. Thus, in addition to latency and area, energy is a key performance metric. Our earlier work has focused on a highlevel modeling technique, domain specific modeling, and a methodology for energy-efficient design of application kernels using FPGAs [1, 5]. In this paper, we discuss an estimation and simulation framework for energy and latency estimation for application designs using platform FPGAs. The framework discussed in this paper is an extension of the MILAN design environment [3]. MILAN is a Model based Integrated simuLAtioN framework for embedded system design and optimization through integration of various simulators into a unified environment. Using the MILAN framework, a designer formally models the target application and architecture. The information captured in the models are used to drive various simulators from a single interface. MILAN is an extensible framework where the modeling capability can be extended to support additional domains and integrate additional simulators. The extension of MILAN, discussed in this paper, modifies the modeling paradigm to support modeling of designs using Platform FPGAs, develops a performance estimator for kernel designs, and integrates simulators specific to the Platform FPGAs. We also enhance HiPerE, a high-level, system-wide, performance estimator to support Platform FPGAs [6]. The framework discussed in this paper adopts Model Integrated Computing (MIC) as the core design philosophy [2]. MIC advocates the extension of the scope and use of models so that they form the backbone of system development. For a given domain (e.g. platform FPGAs), using integrated multiple-view models to capture all aspects (application, resource, behavior, constraints, etc.) of a system it is possible to drive various tools and simulators using a single model. The Generic Modeling Environment (GME) is a configurable graphical tool suite supporting MIC [2]. GME is configured through the use of metamodels which contain syntactic, semantic, and presentation specifications of the target domain [2]. Model Interpreters (MI) are tool specific software components that translate the information captured in the models into the format required by the tools enabling tool-integration. 2. Estimation and Simulation Framework The framework consists of three modules, integrated simulation module, kernel specification module, and system-level design module (Figure 1). A. Integrated Simulation Module This module integrates a set of widely used power and latency simulators available for platform FPGAs. The inputs to this module are specifications in HDL or C and appropriate input stimulus (both generated from the models) and the outputs are various performance estimates. The HDL or C specification is generated based on the model of the hardware and application respectively [3]. Currently, the framework targets the Xilinx Virtex-II Pro [8]. The specific simulators and related tools that are (being) integrated into the Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’03) 1082-3409/03 $17.00 © 2003 IEEE framework are ModelSim and Power Estimator, XPower, XST, and Place and Route tools from Xilinx [4, 8]. For PowerPC simulation, we are currently using ModelSim and GDB Insight. All the tools are driven from a single modeling paradigm. Additional simulators can be easily integrated by writing appropriate MIs which makes the framework plug-n-play. To improve accuracy, we simulate each design a number of times with randomly generated input waveforms with varying levels of switching activity and evaluate the average latency and energy using a confidence interval for statistically significant results. We have also integrated two performance estimators, Kernel Performance Estimator and HiPerE, that are discussed in the following sections.